A 16 Core Processor With Hybrid Inter-Core Communication

A 16-core processor with hybrid (i.e., both message-passing and shared-memory) inter-core communication mechanisms are implemented in 90nm CMOS. Shared-memory communication is supported using the shared memory within each cluster and Message-passing communication is enabled in a 3× 6 Mesh packet-switched network-on-chip. The proposed system consists of a direct memory to memory communication between two clusters which is implemented by using a DMA prototype. The prototype is especially designed for specific functionality. It is observed that the communication time between the source and destination is 620ns in case of shared-memory communication and it gets reduced to 450ns in case of message-passing communication. Compared to shared-memory and message-passing communications the proposed system reduces the communication time to 330ns. Three types of communications are implemented in XILINX 12.2 version software.